Input level translators are generally used in CMOS integrated circuit (IC) input buffers to convert TTL signals to CMOS signals that are utilized within the IC. Specifically, the input level translator converts TTL signals which typically have low voltage levels of eight-tenths (0.8) volts and high voltage levels of two (2) volts to CMOS signal levels having V.sub.ss as a logical zero and V.sub.cc as a logical one.
This signal level conversion is necessary because the TTL levels are not stable enough to provide for the transitions required for CMOS circuits. In a input buffer circuit, the input level translator is followed by a driver circuit. This driver then drives the TTL levels to the appropriate CMOS levels for use by the IC. Accordingly, the input level translator circuit translates the input signal, and the driver circuit drives the translated input signal to the output of the input buffer.
Normally, the translator is an inverter which is ratioed in such a manner that a low TTL signal (0.8 volts or less) provides a high CMOS output and a high TTL signal (2 volts or more) provides a low CMOS output. What is meant by ratioed is that the width to length ratio of the transistors within the level translators are sized in such a fashion in order to provide the appropriate level translator.
Thus, the level translator and the CMOS circuit driver are ratioed in such a fashion as to achieve the desired output levels with appropriate applied input, in order to provide full CMOS levels to all the subsequent stages. If the translation's edge rate is not sharp, then in subsequent stages of the CMOS circuit, the circuit will stay on for a longer period of time. Hence, a typical CMOS circuit experiences a DC power drain due to the circuit having a DC path to V.sub.ss, and an attendant loss of effectiveness.
CMOS circuits are oftentimes required to be in a "sleep" or "standby" mode in which the circuit is powered down. This is done to conserve power in an environment where power saving is a priority. When a CMOS circuit is in a sleep mode, the power used by the IC is significantly lower than that consumed during normal operation and the internal gates and buffers of the circuit retain the state that they had when the circuit was active.
If the circuit is in the sleep mode, the input translator circuit of the input buffer circuit must also be in sleep mode. If not powered down, the input translator circuit will draw DC and ac switching currents. In the prior art, sleep mode is accomplished by utilizing a "NAND" gate or a "NOR" gate to receive a disabling or an enabling signal to place the IC into sleep or active condition respectively.
Although the input buffer circuit is in the sleep mode, when the level translator becomes inactive and drawing no active power, a minute amount of leakage current is still drawn in the form of "sub threshold" and "p-n" junction leakage currents within the input level translator.
Another problem such input level translator circuits face is that the perturbations from the power supply may cause erroneous switching problems at the output of the CMOS circuit. Additionally, a third problem may result when, for example, noise on the input signal causes a change in the output. For instance, when the input signal level may be at some intermediate level between V.sub.IL and V.sub.IH, an unwanted change in the output signal may occur. Therefore, it is important to ensure that the changes occur at either V.sub.IL or V.sub.IH at all times.
Therefore, it is desirable to provide an input buffer circuit that includes an input level translator which overcomes the DC power drain and noise-sensitive switching problems of previously known level translator circuits. It is also desirable to have such a circuit that includes a sleep function that reduces power when the IC is in a standby or power-down mode.